1. Field of the Invention
This invention relates to high-voltage integrated circuit devices.
2. Related Arts
High-voltage integrated circuits (HVICs) are well known as means for on-off driving of switching power devices forming the upper arms of bridge circuits for power inversion (DC-AC conversion) such as PWM inverters. Recently, element separation-type HVICs using high-voltage junctions, not requiring potential insulation by a transformer, photocoupler or similar, have been adopted to enhance functionality of switching power devices through overcurrent detection and temperature detection when an abnormality occurs, and to decrease the size and reduce the costs of power supply systems.
FIG. 9 is an explanatory diagram showing an example of connection of switching devices forming an inverter or other power conversion device and a conventional HVIC which drives the devices. FIG. 9 shows an example of a half bridge in which two switching devices (here, IGBTs (insulated gate bipolar transistors) 114 and 115) are connected in series. The power conversion device shown in FIG. 9 outputs a high potential or a low potential in alternation from the Vs terminal, which is the output terminal, by turning on the upper-arm IGBT 115 and the lower-arm IGBT 114 of the half-bridge in alternation, to supply AC power to the L load 118.
That is, when outputting high potential, the IGBT 114 and IGBT 115 are made to operate such that the upper-arm IGBT 115 is turned on and the lower-arm IGBT 114 is turned off. On the other hand, when outputting low potential, the IGBT 114 and IGBT 115 are made to operate such that the upper-arm IGBT 115 is turned off and the lower-arm IGBT 114 is turned on. The diodes connected to be antiparallel with the IGBTs 114 and 115 are free wheel diodes (FWDs) 116 and 117.
During an operation interval, in the driving element HVIC 111 a GND-reference gate signal is output from L-OUT to the lower-arm IGBT 114, and a gate signal with the Vs terminal potential as reference is output from H-OUT to the upper-arm IGBT 115. A signal with the Vs terminal potential as reference is output from H-OUT, and so the HVIC 111 must be provided with a level shift function.
Among the symbols in FIG. 9, Vss indicates the high-potential side of the high-voltage power supply (main circuit power supply), and GND is ground. Vs is an intermediate potential, fluctuating from the Vss potential to GND potential. H-VDD is the high-potential side of the low-voltage power supply 113 which takes the Vs terminal potential as reference. L-VDD is the high-potential side of the low-voltage power supply 112 which takes GND as reference.
H-IN is the input signal and input terminal for input to the gate of the CMOS circuit on the low side connected with a level-raising circuit. L-IN is the input signal and input terminal for input to the gate of the CMOS circuit on the low side connected with the gate of the lower-arm IGBT 114.
As explained above, H-OUT is the output signal and output terminal of the high-side CMOS circuit which is output to the gate of the upper-arm IGBT 115. L-OUT is the output signal and output terminal which is output to the gate of the lower-arm IGBT 114.
ALM-IN is the input signal and input terminal for a detection signal 119 when temperature and overcurrent of the upper-arm IGBT 115 are detected. ALM-OUT is the output signal and output terminal of the detection signal with level lowered.
FIG. 10 and FIG. 11 are circuit diagrams of a level shift circuit and peripheral circuits. FIG. 10 is a circuit diagram including a level-raising circuit, and FIG. 11 is a circuit diagram including a level-lowering circuit. In FIG. 10 and FIG. 11, the symbol 120 indicates the terminal on the high-potential side of the low-voltage power supply 113 with the Vs terminal as reference. In this Specification and the attached drawings, layers and regions modified by “n” or “p” have electrons and holes, respectively, as the majority carriers. Moreover, an “n” or “p” modified by a “+” or “−” indicates that the impurity concentration is higher and lower, respectively, than in a layer or region without these symbols.
As the peripheral circuits, a low-side CMOS circuit (PMOS and NMOS) which transmits the input signal of the level-shift circuit (low-side circuit portion), and a high-side CMOS circuit (PMOS and NMOS) which transmits the output signal (output from the output portion 101) of the level-shift circuit (level-raising circuit or level-lowering circuit) to the upper-arm IGBT 115 (high-side circuit portion), are shown. The symbol 71 in FIG. 10 is a level-shifting resistor. The symbol 75 is a diode which raises the voltage of a bootstrap capacitor, not shown, and is a bootstrap diode which products a higher voltage by the amount of the bootstrap voltage (equivalent to the voltage of the low-voltage power supply 113) than the voltage Vs. The voltage of this low-voltage power supply 113 and the voltage of the low-voltage power supply 112 are the same.
In FIG. 10, when an input signal (H-IN) is input to the low-side circuit portion, the signal passes through the CMOS circuit of the low-side circuit portion and is input to the gate of the n-channel MOSFET 41 of the level-raising circuit. This signal turns the n-channel MOSFET 41 on and off, the output signal of the level-raising circuit is output from the output portion 101, and by means of this signal the CMOS circuit of the high-side circuit portion is turned on and off and the output signal (H-OUT) is output. This output signal is converted into a signal which takes the Vs terminal potential as reference. The output signal is input to the gate of the upper-arm IGBT 115, and the upper-arm IGBT 115 is turned on and off. The level-raising circuit in FIG. 10 is necessary when the upper-arm IGBT 115 is an n-channel device.
In FIG. 11, the level-lowering circuit is formed of a p-channel MOSFET 43 and a level-shifting resistor 72. A diode 76 is connected in parallel with the level-shifting resistor 72. The ALM-IN signal is input to the gate of the CMOS circuit of the high-side circuit portion, and the output signal of the CMOS circuit is input to the gate of the p-channel MOSFET 43 of the level-lowering circuit. By this means, the p-channel MOSFET 43 is turned on and off. By turning the p-channel MOSFET 43 on and off, a signal is output from the output portion 102 of the level-lowering circuit to the low side (low-side circuit portion). And, the level-lowered ALM-OUT signal from the output of the CMOS circuit of the low-side circuit portion is output from the low-circuit circuit portion as a detection signal.
In the HVIC 111 shown in FIG. 9, terminals for input/output of each of the signals described above (H-VDD, H-OUT, ALM-IN, L-VDD, L-OUT, GND, H-IN, ALM-OUT and L-IN) are shown. These correspond to the terminals in FIG. 10 and FIG. 11.
Bridge circuits created by combining half-bridge circuits formed using the switching devices (IGBTs 114 and 115) shown in FIG. 9 are widely in numerous fields, such as in home-use inverters for large-capacity PDPs (Plasma Display Panels), liquid crystal panels and other power supply applications, air conditioners and lighting, in addition to inverters for motor control.
Because such motors, lighting and similar become inductive loads (L loads) 118 such as shown in FIG. 9, there is an effect of parasitic inductance components and similar due to wiring on the printed circuit board, the cable up to the L load 118 and similar. That is, when the IGBT 115 of the upper arm is turned off, and when switching so that the lower-arm IGBT 114 is turned on, there is a shift to the negative-potential side relative go ground potential (the potential of the GND terminal in FIG. 9) of the potential at the Vs terminal which is the high-potential side reference potential of the high-side circuit portion forming the HVIC 111 and the potential of the H-VDD terminal.
This shift to the negative-potential side (negative surge voltage) causes erroneous operation and latchup of the high-side circuit portion, and consequently there is the concern that the HVIC 111 may be destroyed. FIG. 12 is a circuit diagram showing in detail the level-shifting circuit of a conventional high-voltage integrated circuit device. FIG. 12(a) is the level-raising circuit diagram, and FIG. 12(b) is the level-lowering circuit diagram.
The level-raising circuit shown in FIG. 12(a) is provided with a level-shifting resistor 71, and an n-channel MOSFET 41 the drain of which is connected to the level-shifting resistor 71; the portion connecting the level-shifting resistor 71 and the n-channel MOSFET 41 is an output portion 101 of the level-raising circuit.
In order to prevent destruction of the level-shifting resistor 71 when the H-VDD potential goes to a much lower potential than GND potential (when an excessive negative surge voltage has been applied), a diode 75 is connected in parallel with the level-shifting resistor 71.
Further, the diode 75 functions to prevent the application of an excessive voltage to the gate of the MOSFET of the CMOS circuit of the high-side circuit portion when an overvoltage is applied to the H-VDD terminal. Normally a Zener diode is often used as this diode 75. Further, the n-channel MOSFET 41 incorporates a body diode 42 connected to be antiparallel.
On the other hand, the level-lowering circuit shown in FIG. 12(b) is provided with a drain of a p-channel MOSFET 43 and a level-shifting resistor 72 connected to the drain; the portion connecting the level-shifting resistor 72 and the p-channel MOSFET 43 being an output portion 102 of the level-lowering circuit.
In order to prevent destruction of the level-shifting resistor 72 when the H-VDD potential goes to a much lower potential than GND potential, a diode 76 is connected in parallel with the level-shifting resistor 72.
Further, the diode 76 functions to prevent the application of an excessive voltage to the gate of the MOSFET of the CMOS circuit of the low-side circuit portion when an overvoltage is applied to the H-VDD terminal while the MOSFET 43 is turned on. Further, the n-channel MOSFET 43 incorporates a body diode 44 connected to be antiparallel.
FIG. 13 is a cross-sectional view showing principal portions of the logic portion of the high-side circuit portion, the logic portion of the low-side circuit portion, and the level-raising circuit portion, of a self-isolated high-voltage integrated circuit device. In FIG. 13, an n− region 2 and an n region 3, which are n-well regions, are formed in the surface layer of the p-type semiconductor substrate 1 connected to GND potential. In the n− region 2 is formed, for example, a CMOS circuit or similar forming the logic portion of the low-side circuit portion 91. In the n region 3 is formed, for example, a CMOS circuit or similar forming the level-shifting circuit portion 94 and the logic portion of the high-side circuit portion 92.
The n-channel MOSFET 41 for level shifting (here, level raising) is formed of a p region 51 in contact with the n− region 4 and serving as a base region, an n+ region 53 which is the source and p contact region 54 formed in the p region 51, an n+ region 52 which is the drain formed in the n− region 4, and a gate electrode 55 formed between the n+ region 53 and the n+ region 52 on the p region 51 with a gate oxide film intervening.
In FIG. 13, the symbols 22 and 32 represent n+ regions, and the symbols 28 and 38 represent p+ regions. The symbol 56 represents a p+ region which is a first contact region, the symbol 62 represents an n+ region which is a second contact region, and the symbol 93 represents a high-voltage junction terminating region. The symbols 45 and 46 are pn diodes, and the symbols a to j are electrodes.
In FIG. 12 and FIG. 13, the n+ region 52 which is the drain of the n-channel MOSFET 41 is connected to the H-VDD terminal, via the level-shifting resistor 71, by surface metal wiring. Further, the portion connecting the n+ region 52 which is the drain and the level-shifting resistor 71 is the output portion 101 of the level-raising circuit. This output portion 101 outputs a low potential when the n-channel MOSFET 41 for level shifting is turned on, and outputs a high potential when the MOSFET 41 is turned off, and so can perform level-shifting operation which is signal transmission between different reference potentials.
In this way, a negative surge voltage VS0 which is a negative potential relative to ground potential is applied to the Vs terminal with the timing at which the upper-arm IGBT 115 is turned off. This negative surge voltage VS0 can be calculated using the following equation (1). In equation (1), L0 is the inductance value of the L load 118, and I is the value of the current flowing in the IGBT 115.VS0=L0×dl/dt  (1)
Further, when a negative surge voltage VS0 is lower than GND potential (0 V)−(Vspy+Vfd), the parasitic pn diodes 45 and 46 of the HVIC 111 (chip) begin to conduct. Here Vspy is the battery voltage across the terminals of the high-side low-voltage power supply 113 or a bootstrap capacitor, not shown, and Vfd is the forward-direction voltage drop across the parasitic pn diodes 45 and 46. When the absolute value of a negative surge voltage VS0 is greatly increased in the negative direction, an overcurrent flows in the HVIC 111 (chip), and as a result erroneous operation of the high-side circuit portion tends to occur, and there is the concern that failure or destruction of the HVIC 111 (chip) may occur.
The applied negative surge voltage VS0 is proportional to the product of the parasitic inductance component (L1) of the wiring on the printed circuit board and the cable up to the L load 118 and similar, and dl1/dt due to the turn-off interval of the on current I1 which had been flowing in the IGBT 115 (L1×(dl1/dt)); this spike-shape negative surge voltage VS0 is applied to the Vs terminal. The applied voltage is approximately −100 V, and the applied interval is approximately several hundred nanoseconds to 1 μs.
As such a high-voltage integrated circuit, circuits to protect high-voltage integrated circuits which drive power transistors in a half-bridge configuration have been disclosed. Such a circuit is intended for use with circuits for which excessive negative swings at the output node are anticipated, and is a high-voltage integrated circuit chip having, between the circuit board and ground, a resistor which limits currents during negative voltage spikes. See, for example, Japanese Patent No. 3346763 (also referred to herein as “Patent Reference 1”).
Further, as a high-voltage integrated circuit device, a driving device which diminishes the effect of reverse bias by inserting a diode between the drain electrode of a switching element belonging to a level shifter and the gate electrode of a MOS transistor belonging to an amplifier (CMOS circuit) has been disclosed. See, for example, Japanese Patent Application Laid-open No. 2001-25235 (also referred to herein as “Patent Reference 2”).
Further, as another high-voltage integrated circuit device, a device in which the drain of a switching element belonging to a level shifter, a level-shifting resistor, and a current-limiting resistor are connected in series, and the section from the level-shifting resistor to the current-limiting resistor is taken to be the output portion of a level-raising circuit, has been disclosed. See, for example, Japanese Patent Application Laid-open No. 2008-301160 (also referred to herein as “Patent Reference 3”).
Further, as another high-voltage integrated circuit device, the following device has been disclosed. Adjacent to a p well to form an n-channel MOSFET in CMOS logic among a high-side circuit portion formed of an n well formed on a p substrate, a p+ impurity region is formed and is connected to a potential Vs. An n+ impurity region and p+ impurity region are similarly provided on an n well connected to an H-VDD potential. These impurity regions are formed on the periphery of the high-side CMOS logic, so that the hole current flowing from a ground potential region into the high-side n well region is absorbed before flowing into the p well, and parasitic thyristor latchup arising from a negative surge voltage can be avoided. See, for example, Japanese Patent Application Laid-open No. 2009-147378 (also referred to herein as “Patent Reference 4”).
However, the above-described high-voltage integrated circuit devices of the prior art have the following problems. In the connection of a switching power device and an HVIC shown in FIG. 9, when the Vss voltage is approximately 1200 V and the H-VDD potential is approximately 20 V higher than the potential Vs, if the upper-arm IGBT 115 operates and the lower-arm IGBT 114 is turned off, current flows from the upper-arm IGBT 115 to the L load 118.
When, from this state, the upper-arm IGBT 115 is turned off, the L load 118 attempts to maintain the current, and so current flows from GND via the lower-arm FWD 116, the potential at the Vs terminal becomes lower than GND potential, and may reach approximately −100 V. When the potential at the Vs terminal reaches approximately −100 V, the potential at the H-VDD terminal is approximately −80 V.
In the structure of a high-voltage integrated circuit device shown in FIG. 13, the p semiconductor substrate 1 and the p region 61 are at GND potential. Hence when the potential at the Vs terminal is lowered until both the n region 3 which is an n well region and the n− region 4 which is an n− well region are lower than GND potential, both the parasitic pn diode 45 formed of the p semiconductor substrate 1 and the n region 3, and the parasitic pn diode 46 formed of the p region 61 and the n− region 4 are biased in the forward direction, and a large current flows.
Due to this large current, erroneous operation of the HVIC high-side circuit portion and low-side circuit portion may occur, and destruction due to latchup may occur. In this regard, the above-described Patent Reference 1 does not mention connection of a resistor which limits current between a ground terminal and the substrate, or connection at other places. Because this resistor is formed in a polysilicon layer, when a large pulse current (several Amperes to several tens of Amperes) due to a negative surge voltage flows transiently in a parasitic diode between the Vs terminal and the ground terminal, there is the concern that the polysilicon layer may be thermally decomposed by the overcurrent, leading to destruction of the HVIC.
Further, in the above-described Patent Reference 2, a diode is connected to diminish the effect of reverse biasing, and there is no mention of a resistor or layout method to limit the current in a body diode or parasitic diode when the H-VDD potential is at a more negative potential than the L load.
Further, in the above-described Patent Reference 3, it is proposed that by connecting a current-limiting resistor in the path between the high-potential side (H-VDD) and the low-potential side (ground) of the low-voltage power supply with reference voltage Vs of the level-shifting circuit, destruction by overcurrent of the body diode of an n-channel MOSFET and a parasitic diode themselves, and destruction by overcurrent at places in the level-shifting circuit at which the current capacity is small, are prevented. However, there is no mention of prevention of parasitic erroneous operation (erroneous inversion) of the Vs-reference high-side logic (CMOS circuit) or ground-reference low-side logic (CMOS circuit).
Further, in the above-described Patent Reference 4, it is stated that the n+ and p+ impurity regions in the high-side well region are fixed at H-VDD potential and VS potential to prevent parasitic erroneous operation of the Vs-reference high-side logic due to a negative surge voltage. However, there is no mention of prevention of erroneous operation of the logic portion of the low-side circuit portion.
FIG. 14 is an explanatory diagram showing erroneous operation of the low-side circuit portion and high-side circuit portion of a high-voltage integrated circuit device of the prior art. The cross-sectional configuration of the HVIC shown in FIG. 14 corresponds to the HVIC cross-sectional configuration shown in FIG. 13, and is the cross-sectional configuration of the low-side circuit portion 91, high-voltage junction terminating region (HVJT) 93, and high-side circuit portion 92. However, in FIG. 14, the level-raising circuit shown in FIG. 13 is omitted.
When a negative surge voltage is input to the H-VDD terminal via the Vs terminal, a forward-direction current flows in the parasitic pn diode 46. At this time, electrons, which are the minority carrier, are injected from the n− region 4 into the p region 61 which is the p anode region of the parasitic pn diode 46. The electrons flow into the n− region 2 with hardly any electrons being pulled out from the p+ region 56 which is the first contact region formed in the p region 61, and flow toward the n+ region 22, at a higher potential of for example approximately 15 V.
In this process, due to a parasitic resistance 78 existing in the n− region 2 which is an n well region in which the low-side circuit portion 91 is formed, the potential of the n− region 2 below the p+ region 24 which is the drain of the p-channel MOSFET forming the logic portion of the low-side circuit portion 91 is pulled down by the voltage drop.
As a result, in the low-side circuit portion 91 also, a parasitic pnp bipolar transistor 79, which has as emitter the p+ region 24 which is the drain of the p-channel MOSFET forming the logic portion, has as a base the n− region 2, and has as a collector the p semiconductor substrate 1, is turned on. Consequently, there is the concern that erroneous operation such as inversion of the output logic of the L-OUT terminal, and destruction resulting from latchup of the low-side circuit portion 91, may occur.
On the other hand, minority carrier holes which have entered into the n− region 4 flow into the p+ regions 33 and 34 which are the source and drain of the p-channel MOSFET forming the logic portion of the high-side circuit portion 92, and flow into the p region 31 which is a p offset region. As a result, a parasitic npn transistor formed of the n+ region 37 which is the source of the n-channel MOSFET, the p region 31 which is a p offset region, and the n region 3, is turned on, and there is the concern that erroneous operation of the logic portion of the high-side circuit portion 92 and destruction resulting from latchup may occur. In FIG. 14, the symbols 25, 29, 35 and 39 each indicate a gate electrode.
Thus, as described above, there are certain shortcomings in the related art.